DDR PHY
Dolphin Technology now provides customers with a DDR PHY Interface(DFI) solution.
We now provide a complete DDR Memory Controller Solution.
- Features
- Design Status
- Silcion Status
- Dolphin DDR2/DDR3 PHY IP is fully compliant with the DFI 2.1 Specification
- Support speeds of up to 2133Mbps with 1.8V oxide and 1600Mbps with 2.5V Oxide.
- IP is split into 2 hard macros.
One for commands, control and address pins and another for 8-bit data bus.
Can support custom number of address bits. - Compensation controller and Pads are provided for automatic driver and receiver termination impedance calibration
- Features include slew rate control, Per-bit de-skew, gate training, read and write leveling.
- JTAG signals also provided for Mentor/Synopsys and LogicVision
- Built in Self Test with a Pseudo Random Pattern Generator
- Built with Scannable flops
- Can be used in wirebond, flip-chip and cup configurations
- Front End views are
- available under NDA
- In silicon
- Copyright © 2011 Dolphin Technology, Inc. All rights reserved
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