Memory Controller
Dolphin Technology offers a high performance DDRx/LPDDRx DRAM memory controller solution.
- Features
- Optimized to provide a complete solution along with the Dolphin Technology DDR PHY solution
- DFI 2.1 Interface with Matching or 1:2 Frequency Ratio
- Built-in Gate Training, Read/Write Leveling Functionality
- Supports speeds of up to 2133Mbps
- Support for JEDEC Standard DDR3, DDR2, and LPDDR2 SDRAM
- Multi-Port Configurable AXI4 Interface with QoS Signaling
- Fully compliant with DDR PHY Interface (DFI) 2.0 Specification, and compatible with DTI PHY.
- Multi-port arbitration engine with programmable dynamic priority algorithm ensure high performance and low-latency.
- Pipeline Option for Frequency versus Latency Tradeoff
- Supports core speed up to 1066MHz on TSMC 40G process.
- Fully configurable for various performances and requirements, ensuring maximum performance for different system environments.
- FPGA portable. Compatible with Xilinx PHY and Altera PHY.
- Available with BFM verification suite.
- Single AXI4-Lite Programming Interface
- Support for AXI4 Dynamic QoS Signaling for Non-Blocking Communications
- Support for Low-Latency Bypass Ports/Channels
- Advanced Dynamic QoS Support Based on the Queuing Theory and Traffic Hysteresis
- Forward Priority Propagation for Queued Transactions
- Traffic-Configurable Address Mapping Scheme with Two Column Segments
- Run-time Configurable Timing Parameters and Memory Settings
- Intelligent Bank Management and Auto-Precharge Scheduling
- Intelligent Traffic Direction Aggregation and Switching
- Programmable and Dynamic Auto-refresh Scheduling
- Proprietary Non-Blocking Priority-Based DDRx/LPDDRx SDRAM Control and Data Buses Access Algorithm
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