I/O Products
Standard I/O (GPIO)
Dolphin Technology offers a wide
range of I/O that consists of standard LVCMOS/LVTTL I/O, bus
interface specific (special) I/O as well as high speed I/O.
The variety of our I/O offering provides our customers with a
complete range of I/O solutions. We specialize in Staggered,
Inline, and Flip-Chip (C4) pads with aggressive pitch for the
most demanding designs, whether pad limited or core limited.
Our standard I/O include built in JTAG for testability and
include a broad range of drive strength, slew rate control,
pull-up, pull-down and sustain
| Standard I/O |
| Technology |
Foundry |
Process |
Description |
Design Status |
Silicon Status |
|
65nm
|
TSMC
|
G |
- Staggered pad design with 30um
pitch
- Core/Area I/O pads for Flip-Chip
FC/C4 175um, 200um and 225um
- LVCMOS, LVTTL & Schmitt Trigger input
- I/O Drive strengths 2/4/6/8/10/12/16 mA
1.0V(G)/1.2V(GT/OD) core with 2.5V Xtrs, 2.5V
output Drive
- I/O Drive strengths 2/4/6/8/10/12/16 mA
1.0V(G)/1.2V(GT/OD) core with 2.5V Xtrs, 2.5V output
Drive/3.3V
tolerant
- I/O Drive strengths 2/4/6/8/10/12/16 mA
1.0V(G)/1.2V(GT/OD) core with 2.5V Xtrs, 3.3V output
Drive Capable
- I/O Drive strengths 2/4/6/8/10/12/16 mA
1.0V(G)/1.2V(OD) core with 3.3V Xtrs, 3.3V output
Drive/5.0V
tolerant
- Pull-up, pull-down, sustain level options
- 4 different slew rate keeper options
- Built-in JTAG Logic for testability (LogicVision,
Mentor or Synopsys compatible).
- Level shifts from 1.0V/1.2V core up to 3.3V
I/O supply and from 3.3V to 1.2V
|
Front End views are available under NDA
|
|
|
90nm
|
TSMC |
G
GT
LP
|
- Staggered pad design with 30um
pitch
- Core/Area I/O pads for Flip-Chip
FC/C4 175um, 200um and 225um
- LVCMOS, LVTTL & Schmitt Trigger input
- I/O Drive strengths 2/4/6/8/10/12/16 mA
1.0V(G)/1.2V(GT/OD) core with 2.5V Xtrs, 2.5V
output Drive
- I/O Drive strengths 2/4/6/8/10/12/16 mA
1.0V(G)/1.2V(GT/OD) core with 2.5V Xtrs, 2.5V output
Drive/3.3V
tolerant
- I/O Drive strengths 2/4/6/8/10/12/16 mA
1.0V(G)/1.2V(GT/OD) core with 2.5V Xtrs, 3.3V output
Drive Capable
- I/O Drive strengths 2/4/6/8/10/12/16 mA
1.0V(G)/1.2V(OD) core with 3.3V Xtrs, 3.3V output
Drive/5.0V
tolerant
- Pull-up, pull-down, sustain level options
- 4 different slew rate keeper options
- Built-in JTAG Logic for testability (LogicVision,
Mentor or Synopsys compatible).
- Level shifts from 1.0V/1.2V core up to 3.3V
I/O supply and from 3.3V to 1.2V
|
"G"
Test Chip Taped Out (Q3 2004)
"GT" Test Chip Taped Out (Q4 2004) |
Working Silicon in Customer Design
&
G/GT Working Silicon in Dolphin
Test-Chip
(Test-chip report is available )
|
| IBM |
9SF |
|
|
| 0.13um |
TSMC |
LV
LVOD
G |
- Staggered pad design with 30um
pitch
- Core/Area I/O pads for Flip-Chip
FC/C4 200um & 225um
- LVCMOS, LVTTL & Schmitt Trigger input
- I/O Drive strengths 2/4/6/8/10/12/16 mA
1.0V(LV)/1.2V(HS/G) core with 2.5V output
- I/O Drive strengths 2/4/6/8/10/12/16 mA
1.0V(LV)/1.2V(HS/G) core with 2.5V output /3.3V
tolerant
- I/O Drive strengths 2/4/6/8/10/12/16 mA
1.0V(LV)/1.2V(HS/G) core with 3.3V output
- I/O Drive strengths 2/4/6/8/10/12/16 mA
1.0V(LV)/1.2V(HS/G) core with 3.3V output /5.0V
tolerant
- Pull-up, pull-down, sustain level options
- 4 different slew rate keeper options
- Built-in JTAG Logic for testability (LogicVision,
Mentor or Synopsys compatible).
- Level shifts from 1.0V/1.2V core up to 3.3V
I/O supply and from 3.3V to 1.2V
|
Taped Out (Nov 2002)
|
Working Silicon in Customer Design
&
LV/LVOD Working Silicon in Dolphin
Test-Chip (Test-chip
report is available)
|
| UMC |
HS SP |
|
Working Silicon In Customer Design
|
| IBM |
8SF |
|
Working Silicon In Customer Design
|
0.18um |
TSMC |
G |
- Staggered pad design with 35, 50, 70
um pitch
- I/O pads for Flip-Chip FC/C4 240
& 250um
- I/O Drive strengths 2/4/6/8/10/12/16 mA,
1.8V core with 3.3V output
- Pull-up, pull-down, sustain level options
- 4 different slew rate keeper options
- Built-in JTAG Logic for testability (LogicVision,
Mentor or Synopsys compatible).
- Schmitt trigger inputs
- Level shifts from 1.8V core up to 3.3V I/O
supply
|
|
Working Silicon In Customer Design
|
| UMC |
LOGIC |
|
Working Silicon In Customer Design
|
| IBM |
7SF |
|
Working Silicon In Customer Design
|
0.25um |
UMC |
LOGIC |
- AGP-4X/2X Backwards compatible, SSTL
- PVT (Process, Voltage, & Temperature)
Compensated I/O Buffer
|
|
Working Silicon In Customer Design
|
|
|
