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I/O Products

Special Purpose I/O's

Dolphin's proven track record in Special I/O design has allowed us to develop exceptional design capabilities and apply them to High Performance I/O designs. We specialize in Staggered, Inline, and Flip-Chip FC/C4 pads with aggressive pitch for the most demanding designs, whether pad limited or core limited. Dolphin Technology offers a wide range of high speed I/O including: HyperTransport^®, DDR-I/DDR-II/GDDR-III/HSTL with On-Die Termination, RLDRAM I, RLDRAM II, SPI4.2, LVDS, LVDS/LVPECL Combo, SSTL2 Class I/II DDR, HSTL Class I/II DDR, LVPECL, PCI Express, PCIX-133, CML, I²C, PCI and so on.

Special Purpose I/O
Technology	Foundry	Process	Description	Design Status	Silicon Status
65nm	TSMC	G	Staggered pad design with 30 um pitch Core/Area I/O pads for Flip-Chip FC/C4 175um, 200um and 225um. LVDS Drivers and receivers with PVT (Process, Voltage and Temperature) Compensation and receivers with PVT Compensated On-Die Termination LVPECL IO with PVT Compensation LVDS/LVPECL Combo with PVT Compensation PCI-X with PVT Compensation at133 MHz operation and backwards compatible with PCI-66/33 MHz HSTL Class I/II DDR I/II, SSTL2 & SSTL18 (Class I/II) & HSTL 1.8V/1.5V combo pad with PVT Compensation and optional PVT compensated internal termination Rtt uptp @400-500MHz/800Mbs-1Gbs RLDRAM I & RLDRAM II SPI4.2 with Dynamic De-Skewing Impedance Matched, Source Series Terminated 1.5V IO (SDR/DDR) with PVT (Process, Voltage and Temperature) compensation Impedance Matched, Source Series Terminated 1.8V IO (SDR/DDR) with PVT Compensation Impedance Matched, Source Series Terminated 2.5V IO (SDR/DDR) with PVT Compensation Impedance Matched, Source Series Terminated 3.3V IO (SDR/DDR) with PVT Compensation SSTL2 & 18 (DDR) Class I/II HyperTransport^TM (LDT) RX/TX/IO macros for licensed AMD K8 bus partners @2.4Gbs PCI-66/33 GTL, GTL+, AGTLP AGP 2X/4X/8X USB 1.1/2.0 GMII, RGMII, XGMII I²C CML	Front End views are available under NDA
90nm	TSMC	G GT LP	Staggered pad design with 30 um pitch Core/Area I/O pads for Flip-Chip FC/C4 175um, 200um and 225um. LVDS Drivers and receivers with PVT (Process, Voltage and Temperature) Compensation and receivers with PVT Compensated On-Die Termination Fully Configurable LVTTL/LVCMOS, PCI 66/PCIX-133 , SSTL3, SSTL2, SSTL18 (Class I/II) with On Die Termination, HSTL1.8V/1.5V (Class I/II) with On Die Termination Fully Configurable LVTTL/LVCMOS, PCI 66/PCIX-133 , SSTL3, SSTL2, SSTL18 (Class I/II) with On Die Termination, HSTL 1.8V/1.5V (Class I/II) with On Die Termination, LVDS Driver and LVDS/LVPECL Receiver with Differential On Die Termination LVPECL IO with PVT Compensation LVDS/LVPECL Combo with PVT Compensation PCI-X with PVT Compensation at133 MHz operation and backwards compatible with PCI-66/33 MHz HSTL Class I/II DDR I/II, SSTL2 & SSTL18 (Class I/II) & HSTL 1.8V/1.5V combo pad with PVT Compensation and optional PVT compensated internal termination Rtt uptp @400-500MHz/800Mbs-1Gbs RLDRAM I & RLDRAM II SPI4.2 with Dynamic De-Skewing Impedance Matched, Source Series Terminated 1.5V IO (SDR/DDR) with PVT (Process, Voltage and Temperature) compensation Impedance Matched, Source Series Terminated 1.8V IO (SDR/DDR) with PVT Compensation Impedance Matched, Source Series Terminated 2.5V IO (SDR/DDR) with PVT Compensation Impedance Matched, Source Series Terminated 3.3V IO (SDR/DDR) with PVT Compensation SSTL2 & 18 (DDR) Class I/II HyperTransport^TM (LDT) RX/TX/IO macros for licensed AMD K8 bus partners @2.4Gbs PCI-66/33 GTL, GTL+, AGTLP AGP 2X/4X/8X USB 1.1/2.0 GMII, RGMII, XGMII I²C CML	"GT" Test Chip Taped Out (Q4 2004) "G" Test Chip Taped Out (Q3 2004)	Working Silicon in Customer Design & G/GT Working Silicon in Dolphin Test-Chip (Test-chip report is available)
90nm	IBM	9SF		Taped Out (Q2 2004)	Working Silicon in Customer Design
0.13um	TSMC	LV LVOD G	Staggered pad design with 30 um pitch Core/Area I/O pads for Flip-Chip FC/C4 200um & 225um LVDS drivers with PVT Compensation and receivers with On-Die Termination LVPECL with PVT Compensation LVDS/LVPECL Combo with PVT Compensation and On-Die Termination PCI-X for 133 MHz operation and backwards compatible with PCI-66/33 MHz with PVT Compensation HSTL Class I/II DDR I/II, SSTL2 & SSTL18 (Class I/II) & HSTL 1.8V/1.5V combo pad with optional PVT compensated internal termination Rtt upto @400MHz/800Mbs RLDRAM I & RLDRAM II SPI4.2 with Dynamic De-Skewing Impedance Matched, Source Series Terminated 1.5V IO (SDR/DDR) with PVT Compensation Impedance Matched, Source Series Terminated 1.8V IO (SDR/DDR) with PVT Compensation Impedance Matched, Source Series Terminated 2.5V IO (SDR/DDR) with PVT Compensation Impedance Matched, Source Series Terminated 3.3V IO (SDR/DDR) with PVT Compensation SSTL2 (DDR) Class I/II HyperTransport^TM (LDT) RX/TX/IO macros for licensed AMD K8 bus partners @1.6Gbs, 2+Gbs PCI-66/33 GTL, GTL+, AGTLP AGP 2X/4X/8X USB 1.1/2.0 GMII, RGMII, XGMII I²C	Taped Out (Nov 2002)	Working Silicon in Customer Design & LV/LVOD Working Silicon in Dolphin Test-Chip (Test-chip report is available) Working Silicon in Customer Design
	UMC	HS SP			Working Silicon In Customer Design
	IBM	8SF			Working Silicon In Customer Design
0.15um	TSMC	LV / G	HyperTransport^TM, GPIO, SSTL2, PCI		Working Silicon In Customer Design
0.18um	UMC	Logic	LVDS, LVTTL, LVPECL, HSTL Class I/II (DDR) PCI-X for 133 Mhz operation and PCI-66/33 Mhz Drive strength buffer with PVT Compensation HyperTransport^TM (LDT) RX/TX Macro @ 1.6Gb/s		Working Silicon In Customer Design
	IBM	7SF			Working Silicon In Customer Design
	TSMC	LV G	DDR-II Combination IO Cell HSTL Class I/II (DDR) SSTL (2) Class I/II (DDR) Drive strength buffer with PVT Compensation HyperTransport^TM (LDT) RX/TX Macro S2K Universal AGP 4X/2X/1X/PCI, LVPECL, (K7 Bus) Open-Drain & Push-Pull I²C		Working Silicon In Customer Design
0.25um	TSMC	G/Logic	AGP-4X/2X Backwards compatible, SSTL Drive strength buffer with PVT Compensation		Working Silicon In Customer Design
0.25um	UMC	G/Logic			Working Silicon In Customer Design

Contact Dolphin Technology Sales for more information.