Products
Memory
I/O
Standard Cell
Structured Arrays
PLL
SERDES
Available Views

Product Documentation

Available Views

Views Available for Memory
  • LVS netlist
  • Layout in GDSII format
  • FRAME ready BBox/GDS
  • Timing Files (.lib)
  • Power Consumption Data (Power Compiler Format)
  • Verilog models
  • VHDL models
  • LEF
  • Antenna LEF
  • Data Sheets

 

Views Available for IO's
  • LVS netlist
  • Layout in GDSII format
  • FRAME ready BBox/GDS
  • Timing Files (.lib)
  • Power Consumption Data (Power Compiler Format)
  • Verilog models
  • VHDL models
  • LEF
  • Antenna LEF
  • Data Sheets
  • IBIS models (IO's)

 

 

Views Available for Standard Cells
  • LVS netlist
  • Layout in GDSII format
  • FRAME ready BBox/GDS
  • Timing Files (.lib)
  • Power Consumption Data (Power Compiler Format)
  • Verilog models
  • VHDL models
  • LEF
  • Antenna LEF
  • Data Sheets
  • Technology Files
  • Wire Load Models
  • Noise Models

Contact Dolphin Technology Sales for more information.

 


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